CC1150-RTY1 datasheet(27/67 Pages) TI1

27 / 67 page

XOSC Stable

CSn

CC1150

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SWRS037B – JANUARY 2006 – REVISED MARCH 2015

CC1150 has a built-in state machine that is used to switch between different operations states (modes).

The change of state is done either by using command strobes or by internal events such as TX FIFO

underflow.

A simplified state diagram, together with typical usage and current consumption, is shown in Figure 5-2.

The complete radio control state diagram is shown in Figure 5-11. The numbers refer to the state number

readable in the MARCSTATE status register. This functionality is primarily for test purposes.

5.11.1 Power On Start-up Sequence

When the power supply is turned on, the system must be reset. This is achieved by one of the two

sequences described in Section 5.11.1.1 or Section 5.11.1.2, that is, automatic power-on reset or manual

reset. After the automatic power-on reset or manual reset it is also recommended to change the signal

that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of

CLK_XOSC/192, but to optimize performance in TX, an alternative GDO setting should be selected from

the settings found in Table 5-10.

5.11.1.1 Automatic POR

A power-on reset circuit is included in the CC1150. The minimum requirements stated in Section 4.7 must

be followed for the power-on reset to function properly. The internal power-up sequence is completed

when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. See Section

10.1 for more details on CHIP_RDYn.

When the CC1150 reset is completed the chip will be in the IDLE state and the crystal oscillator running. If

the chip has had sufficient time for the crystal oscillator and voltage regulator to stabilize after the power-

on-reset, the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is

completed the SO pin will first go high, indicating that the crystal oscillator and voltage regulator is not

stabilized, before going low as shown in Figure 5-12.

Figure 5-12. Power-on Reset

5.11.1.2 Manual Reset

The other global reset possibility on CC1150 is the SRES command strobe. By issuing this strobe, all

internal registers and states are set to the default, IDLE state. The power-up sequence is as follows (see

Figure 5-13):

•

Set SCLK = 1 and SI = 0.

•

Strobe CSn low / high. Make sure to hold CSn high for at least 40 µs relative to pulling CSn low.

•

Pull CSn low and wait for SO to go low (CHIP_RDYn).

•

Issue the SRES strobe on the SI line.

•

When SO goes low again, reset is complete and the chip is in the IDLE state.

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