CC1150-RTY1 datasheet(22/67 Pages) TI1

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0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,.......................

Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again

Length field transmitted. Tx PKTLEN value set to mod(600,256) = 88

Infinite packet length enabled

Fixed packet length

enabled when less than

256 bytes remains of

packet

600 bytes transmitted

CC1150

SWRS037B – JANUARY 2006 – REVISED MARCH 2015

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Figure 5-9. Arbitrary Length Field Configuration

5.8.3

Packet Handling in Transmit Mode

The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the

length byte when variable packet length is enabled. The length byte has a value equal to the payload of

the packet (including the optional address byte). If fixed packet length is enabled, then the first byte written

to the TX FIFO is interpreted as the destination address, if this feature is enabled in the device that

receives the packet.

The modulator will first send the programmed number of preamble bytes. If data is available in the TX

FIFO, the modulator will send the two-byte (optionally 4-byte) sync word and then the payload in the TX

FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO and the

result is sent as two extra bytes at the end of the payload data. If the TX FIFO runs empty before the

complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to

exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has underflowed will not restart

TX mode.

If whitening is enabled, the length byte, payload data and the two CRC bytes will be whitened. This is

done

before

the

optional

FEC/Interleaver

stage.

Whitening

enabled

setting

PKTCTRL0.WHITE_DATA=1.

If FEC/Interleaving is enabled, the length byte, payload data and the two CRC bytes will be scrambled by

the

interleaver,

and

FEC

encoded

before

being

modulated.

FEC

enabled

setting

MDMCFG1.FEC_EN=1.

5.8.4

Packet Handling in Firmware

When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet

has been transmitted. Additionally, for packets longer than 64 bytes, the TX FIFO needs to be refilled

while in TX. This means that the MCU needs to know the number of bytes that can be written to the TX

FIFO. There are two possible solutions to get the necessary status information:

a. Interrupt Driven Solution

–

The GDO pins can be used in TX to give an interrupt when a sync word has been transmitted or

when a complete packet has been transmitted by setting IOCFGx.GDOx_CFG=0x06. In addition,

there are two configurations for the IOCFGx.GDOx_CFG register that can be used as an interrupt

source to provide information on how many bytes that is in the TX FIFO. The

IOCFGx.GDOx_CFG=0x02 and the IOCFGx.GDOx_CFG=0x03 configurations are associated with

the TX FIFO. See Table 5-10 for more information.

b. SPI Polling

–

The PKTSTATUS register can be polled at a given rate to get information about the current GDO2

and GDO0 values respectively. The TXBYTES register can be polled at a given rate to get

information about the number of bytes in the TX FIFO. Alternatively, the number of bytes in the TX

FIFO can be read from the chip status byte returned on the MISO line each time a header byte,

data byte, or command strobe is sent on the SPI bus.

Detailed Description

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