CC1150-RTY1 datasheet(37/67 Pages) TI1

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CC1150

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SWRS037B – JANUARY 2006 – REVISED MARCH 2015

2. Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at

startup and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values in MCU memory. The

VCO capacitance calibration FSCAL1 register value must be found for each RF frequency to be used.

The VCO current calibration value and the charge pump current calibration value available in FSCAL2

and FSCAL3 respectively are not dependent on the RF frequency, so the same value can therefore be

used for all RF frequencies for these two registers. Between each frequency hop, the calibration

process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values that

corresponds to the next RF frequency. The PLL turn on time is approximately 90 µs. The blanking

interval between each frequency hop is then approximately 90 µs.

3. Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge

pump calibration. After writing to FSCAL3[5:4], strobe STX with MCSM0.FS_AUTOCAL=1 for each

new frequency hop. That is, VCO current and VCO capacitance calibration is done, but not charge

pump current calibration. When charge pump current calibration is disabled the calibration time is

reduced from approximately 720 µs to approximately 150 µs. The blanking interval between each

frequency hop is then approximately 240 µs.

There is a trade off between blanking time and memory space needed for storing calibration data in non-

volatile memory. Solution (2) above gives the shortest blanking interval, but requires more memory space

to store calibration values. This solution also requires that the supply voltage and temperature do not vary

much in order to have a robust solution. Solution (3) gives approximately 570 µs smaller blanking interval

than solution (1).

The recommended settings for TEST0.VCO_SEL_CAL_EN change with frequency. This means that one

should always use SmartRF Studio [11] to get the correct settings for a specific frequency before doing a

calibration, regardless of which calibration method is being used. It must be noted that the content of the

CC1150 is not retained in SLEEP state, and thus it is necessary to write to the TEST0 register, along with

other registers, when returning from the SLEEP state and initiating calibrations.

5.19.3 Wideband Modulation Not Using Spread Spectrum

Digital modulation systems under FFC part 15.247 include FSK and GFSK modulation. A maximum peak

output power of 1W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz.

In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in

any 3 kHz band.

Operating at high data rates and frequency deviation the CC1150 is suited for systems targeting

compliance with digital modulation system as defined by FFC part 15.247. An external power amplifier is

needed to increase the output above +10 dBm. Please refer to DN006 [5] for further details concerning

wideband modulation and CC1150.

5.19.4 Data Burst Transmissions

The high maximum data rate of CC1150 opens up for burst transmissions. A low average data rate link

(for example, 10 kBaud), can be realized using a higher over-the-air data rate. Buffering the data and

transmitting in bursts at high data rate (for example, 500 kBaud) will reduce the time in active mode, and

hence also reduce the average current consumption significantly. Reducing the time in active mode will

reduce the likelihood of collisions with other systems in the same frequency range.

5.19.5 Continuous Transmissions

In data streaming applications the CC1150 opens up for continuous transmissions at 500 kBaud effective

data rate. As the modulation is done with a closed loop PLL, there is no limitation in the length of a

transmission (open loop modulation used in some transceivers often prevents this kind of continuous data

streaming and reduces the effective data rate).

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