STM32F0 datasheet(36/71 Pages) STMICROELECTRONICS

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Peripheral migration

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3.14

I2C interface

The STM32F0 series embeds a new I2C peripheral versus the STM32F1 series. The

architecture, features and programming interface are different.

As a consequence, the STM32F0 I2C programming procedures and registers are different

from those of the STM32F1 series, so any code written for the STM32F1 series using the

I2C needs to be rewritten to run on STM32F0 series.

The STM32F0 I2C provides best-in-class new features:



Communication events managed by hardware.



Programmable analog and digital noise filters.



Independent clock source: HSI or SYSCLK.



Wake-up from STOP mode.



Fast mode + (up to 1MHz) with 20mA I/O output current drive.



7-bit and 10-bit addressing mode, multiple 7-bit slave address support with

configurable masks.



Address sequence automatic sending (both 7-bit and 10-bit) in master mode.



Automatic end of communication management in master mode.



Programmable Hold and Setup times.



Command and Data Acknowledge control.

For more information about STM32F0 I2C features, please refer to I2C chapter of

STM32F0xx Reference Manual (RM0091).

3.15

USART interface

The STM32F0 series embeds a new USART peripheral versus the STM32F1 series. The

architecture, features and programming interface are modified to introduce new capabilities.

As a consequence, the STM32F0 USART programming procedures and registers are

modified from those of the STM32F1 series, so any code written for the STM32F1 series

using the USART needs to be updated to run on STM32F0 series.

STM32F0 Datasheet(PDF) 36 Page - STMicroelectronics

STM32F0 Datasheet(HTML) 36 Page - STMicroelectronics

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