STM32F0 datasheet(34/71 Pages) STMICROELECTRONICS

34 / 71 page

Peripheral migration

AN4088

34/71

DocID023072 Rev 3

3.11

PWR interface

In STM32F0 series the PWR controller presents some differences vs. STM32F1 series,

these differences are summarized in the table below. However, the programming interface is

unchanged.

Table 19. PWR differences between STM32F1 series and STM32F0 series

PWR

STM32F1 series

STM32F0x0/x1/x2 devices

STM32F0x8 devices

Power

supplies

1-VDD = 2.0 to 3.6 V: external

power supply for I/Os and the

internal regulator. Provided

externally through VDD pins.

2-VDDA = 2.0 to 3.6 V: external

analog power supplies for ADC,

Reset blocks, RCs and PLL.

VDDA and VSSA must be

connected to VDD and VSS,

respectively.

3-VBAT = 1.8 to 3.6 V: power

supply for RTC, external clock

32 kHz oscillator and backup

registers (through power switch)

when VDD is not present.

1-VDD = 2.0 to 3.6 V: external

power supply for I/Os and the

internal regulator. Provided

externally through VDD pins.

2-VDDA = 2.0 to 3.6 V: external

analog power supplies for ADC,

DAC, Reset blocks, RCs and

PLL. VDDA and VSSA must be

connected to VDD and VSS,

respectively.

3-VBAT = 1.65 to 3.6 V: power

supply for RTC, external clock

32 kHz oscillator and backup

registers (through power switch)

when VDD is not present.

4-VDDIO2 = 0V to 3.6V available

only STM32F07x

1-VDD = 1.8 V +/- 8%: external

power supply for I/Os. Provided

externally through VDD pins.

2-VDDA = 1.65 to 3.6 V: external

analog power supplies for ADC,

DAC, Reset blocks, RCs and

PLL. VDDA and VSSA must be

connected to VDD and VSS,

respectively.

3-VBAT = 1.65 to 3.6 V: power

supply for RTC, external clock

32 kHz oscillator and backup

registers (through power switch)

when VDD is not present.

4-VDDIO2 = 0V to 3.6V available

only STM32F07x

Battery

backup

domain

Backup registers

RTC

LSE

PC13 to PC15 I/Os

Backup registers

RTC

LSE

RCC Backup Domain Control

Backup registers

RTC

LSE

RCC Backup Domain Control

Power

supply

supervisor

Integrated POR / PDR circuitry

Programmable Voltage Detector

(PVD)

Integrated POR / PDR circuitry

Programmable Voltage Detector

(PVD)

Power ON reset must be

controlled externally through the

dedicated NPOR pin.

Low-power

modes

Sleep mode

Stop mode

Standby mode (1.8 V domain

powered-off)

Sleep mode

Stop mode

Standby mode (1.8 V domain

powered-off)

Sleep mode

Stop mode

Wake-up

sources

Sleep mode

– Any peripheral

interrupt/wakeup event

Stop mode

– Any EXTI line event/interrupt

Standby mode

– WKUP pin rising edge

– RTC alarm

– External reset in NRST pin

– IWDG reset

Sleep mode

– Any peripheral

interrupt/wakeup event

Stop mode

– Any EXTI line event/interrupt

Standby mode

– WKUPx pins rising edge

– RTC alarm / autowakeup

– External reset in NRST pin

– IWDG reset

Sleep mode

– Any peripheral

interrupt/wakeup event

Stop mode

– Any EXTI line event/interrupt

1. Same feature but specification change or enhancement

STM32F0 Datasheet(PDF) 34 Page - STMicroelectronics

STM32F0 Datasheet(HTML) 34 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Datasheet Download

Link URL