STM32F0 datasheet(11/71 Pages) STMICROELECTRONICS

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AN4088

Peripheral migration

3.2

System architecture

The STM32F0xx MCU family has been designed to target an entry-level market, with low-

power capabilities and easy handling. In order to fulfill this aim while keeping the advanced

high-end features proper to the STM32, the core has been changed for a ARM® Cortex®-

M0. Its small silicon area, coupled to a minimal code footprint, allows for low-cost

applications with 32-bit performance. Figure 1 shows the correspondence between the

Cortex®-M3 and Cortex®-M0 sets of instructions. Moving from STM32F1 to STM32F0

series requires a recompilation of the code to avoid the use of unavailable features.

Figure 1. System architecture

Important modifications have been performed on the MCU organization too, starting by

switching from a Harvard to Von Neumann architecture, decreasing the system complexity,

or focusing on SW Debug in order to simplify this precise feature.

SYSCFG

Yes

New peripheral

Ethernet

Yes

SDIO

Yes

FSMC

Yes

1. Yes++ = New feature or new architecture,

Yes+ = Same feature, but specification change or enhancement,

Yes = Feature available,

NA = Feature not available

Table 7. STM32 peripheral compatibility analysis, STM32F1 versus STM32F0 series(1) (continued)

Peripheral

STM32F1 STM32F0

Compatibility

Features

Pinout

Firmware driver

STM32F0 Datasheet(PDF) 11 Page - STMicroelectronics