| Electronic Components Datasheet Search |
|
STM32F0 Datasheet(PDF) 15 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32F0 Datasheet(HTML) 15 Page - STMicroelectronics |
|
15 / 71 page ![]() DocID023072 Rev 3 15/71 AN4088 Peripheral migration 70 In addition to the differences described in the table above, the following additional adaptation steps may be needed for the migration. 1. System clock configuration: when moving from STM32F1 series to STM32F0 series, only a few settings need to be updated in the system clock configuration code; mainly the Flash settings (configure the right wait states for the system frequency, prefetch enable/disable) or/and the PLL parameters configuration: a) In case HSE or HSI is used directly as the system clock source, only the Flash parameters should be modified. b) In case PLL (clocked by HSE or HSI) is used as the system clock source, the Flash parameters and PLL configuration need to be updated. Table 10 below provides an example of porting a system clock configuration from STM32F1 to STM32F0 series: – STM32F100x value line running at maximum performance: system clock at 24 MHz (PLL, clocked by the HSE (8 MHz), used as the system clock source), Flash with 0 wait states and Flash prefetch queue enabled. – STM32F0 series running at maximum performance: system clock at 48 MHz (PLL, clocked by the HSE (8 MHz), used as the system clock source), Flash with 1 wait state and Flash prefetch enabled. As shown in Table 10, only the Flash settings and PLL parameters (code in Bold Italic) need to be rewritten to run on STM32F0 series. However, HSE, AHB prescaler and the system clock source configuration are left unchanged, and APB prescalers are adapted to the maximum APB frequency in the STM32F0 series. Note: 1 The source code presented in Table 10 is intentionally simplified (timeout in wait loop removed) and is based on the assumption that the RCC and Flash registers are at their reset values. 2 For STM32F0xx, you can use the clock configuration tool, STM32F0xx_Clock_Configuration.xls, to generate a customized system_stm32f0xx.c file MCO clock source – MCO pin (PA8) – Connectivity Line: HSI, HSE, PLL/2, SYSCLK, PLL2, PLL3 or XT1 – Other product lines: HSI, HSE, PLL/2 or SYSCLK MCO(PA8): SYSCLK, HSI, HSE, HSI14, HSI48, PLLCLK/2, LSE, LSI(1) Int. oscillator measurement / calibration LSI connected to TIM5 CH4 IC: can measure LSI w/ respect to HSI/HSE clock – LSE and LSI clock are indirectly measured through MCO by the timer TIM14 with respect to HSI/HSE clock.(1) – HSI14/HSE are indirectly measured through MCO by means of the TIM14 channel 1 input capture with respect to HSI clock.(1) – HSI48 can be calibrated on the run by the mean of the CRS using a reference clock.(1) 1. Same feature but spec change or enhancement. Table 9. RCC differences between STM32F1 and STM32F0 series (continued) RCC STM32F1 series STM32F0 series |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |