STM32F0 datasheet(16/71 Pages) STMICROELECTRONICS

16 / 71 page

Peripheral migration

AN4088

16/71

DocID023072 Rev 3

containing a system clock configuration routine, depending on your application

requirements.

Table 10. Example of migrating system clock configuration code from STM32F1 to STM32F0

STM32F100x Value Line running at 24 MHz (PLL as

clock source) with 0 wait states

STM32F0xx running at 48 MHz (PLL as clock source)

with 1 wait state

/* Enable HSE ----------------------------*/

RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready */

while((RCC->CR & RCC_CR_HSERDY) == 0)

{

}

/* Flash configuration -------------------*/

/* Prefetch ON, Flash 0 wait state */

FLASH->ACR |= FLASH_ACR_PRFTBE |

FLASH_ACR_LATENCY_0;

/* AHB and APB prescaler configuration --*/

/* HCLK = SYSCLK */

RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK */

RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK */

RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;

/* PLL configuration = (HSE / 2) * 6 = 24 MHz

RCC->CFGR |=

(uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 |

RCC_CFGR_PLLXTPRE_PREDIV1_Div2 |

RCC_CFGR_PLLMULL6);

/* Enable PLL */

RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0)

{

}

/* Select PLL as system clock source ----*/

RCC->CFGR &=

(uint32_t)((uint32_t)~(RCC_CFGR_SW));

RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock

source */

while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS)

!= (uint32_t)0x08)

{

}

/* Enable HSE ----------------------------*/

RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready */

while((RCC->CR & RCC_CR_HSERDY) == 0)

{

}

/* Flash configuration -------------------*/

/* Prefetch ON, Flash 1 wait state */

FLASH->ACR |= FLASH_ACR_PRFTBE |

FLASH_ACR_LATENCY;

/* AHB and APB prescaler configuration --*/

/* HCLK = SYSCLK */

RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

/* PCLK = HCLK */

RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;

/* PLL configuration = HSE*6=48MHz -*/

RCC->CFGR |=

(uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 |

RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);

/* Enable PLL */

RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0)

{

}

/* Select PLL as system clock source ----*/

RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock

source */

while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS)

!= (uint32_t)RCC_CFGR_SWS_PLL)

{

}

STM32F0 Datasheet(PDF) 16 Page - STMicroelectronics

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