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R5F5630ECDFB Datasheet(PDF) 140 Page - Renesas Technology Corp

Part # R5F5630ECDFB
Description  Renesas MCUs
PDF  165 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F5630ECDFB Datasheet(HTML) 140 Page - Renesas Technology Corp

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R01DS0060EJ0100 Rev.1.00
Page 140 of 168
Sep 13, 2011
RX630 Group
5. Electrical Characteristics
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. Cb indicates the total capacity of the bus line.
Figure 5.24
I/O Port Input Timing
Table 5.19
Timing of On-Chip Peripheral Modules (5)
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
Ta = Topr
High drive output is selected by the drive capacity control register.
Item
Symbol
Min.*1,*2
Max.
Unit
Test
Conditions
RIIC
(Fast-mode+)
ICFER.FMPE = 1
SCL input cycle time
tSCL
8 (10) × (1/PCLK) +
240
—
ns
Figure
5.37
SCL input high pulse width
tSCLH
3 (5) × (1/PCLK) + 120
—
ns
SCL input low pulse width
tSCLL
5 × (1/PCLK) + 120
—
ns
SCL, SDA input rise time
tSr
—
120
ns
SCL, SDA input fall time
tSf
—
120
ns
SCL, SDA input spike pulse removal time
tSP
0
4 × (1/PCLK)
ns
SDA input bus free time
tBUF
5 × (1/PCLK) + 120
—
ns
Start condition input hold time
tSTAH
3 (5) × (1/PCLK) + 120
ns
Restart condition input setup time
tSTAS
5 × (1/PCLK) + 120
—
ns
Stop condition input setup time
tSTOS
3 (5) × (1/PCLK) + 120
—
ns
Data input setup time
tSDAS
50
—
ns
Data input hold time
tSDAH
0—
ns
SCL, SDA capacitive load
Cb
—
550
pF
Simple IIC
(Standard-mode)
SDA input rise time
tSr
—
1000
ns
SDA input fall time
tSf
—
300
ns
SDA input spike pulse removal time
tSP
0
4 × (1/PCLK)
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Simple IIC
(Fast-mode)
SCL, SDA input rise time
tSr
20 + 0.1Cb
300
ns
SCL, SDA input fall time
tSf
20 + 0.1Cb
300
ns
SCL, SDA input spike pulse removal time
tSP
0
4 × (1/PCLK)
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Port
PCLK
tPRW



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