R5F5630ECDFB datasheet(137/165 Pages) RENESAS

137 / 165 page

R01DS0060EJ0100 Rev.1.00

Page 137 of 168

Sep 13, 2011

RX630 Group

5. Electrical Characteristics

Note 1. When operation at 3.0 V or a lower voltage is needed, please contact a Renesas sales office.

Note 2. tPcyc: PCLK cycle

Table 5.16

Timing of On-Chip Peripheral Modules (2)

Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V*1, VREFH/VREFH0 = 3.0 V to AVCC0*1,

VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,

PCLK = 8 to 50 MHz,

Ta = Topr

High drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit*2

Test Conditions

RSPI

RSPCK clock cycle

Master

tSPcyc

4096

tPcyc

Figure 5.32

Slave

4096

RSPCK clock high pulse

width

Master

tSPCKWH (tSPcyc – tSPCKR

– tSPCKF) / 2 – 3

—ns

Slave

(tSPcyc – tSPCKR

– tSPCKF) / 2

—

RSPCK clock low pulse

width

Master

tSPCKWL

(tSPcyc – tSPCKR

– tSPCKF) / 2 – 3

—ns

Slave

(tSPcyc – tSPCKR

– tSPCKF) / 2

—

RSPCK clock rise/fall time

Output

tSPCKr,

tSPCKf

—5

Input

—

μs

Data input setup time

Master

VCC

 3.0 V t

—

Figure 5.33 to

Figure 5.36

VCC < 3.0 V

—

Slave

20 – 2 × tPcyc

—

Data input hold time

Master

0—

Slave

20 + 2 × tPcyc

—

SSL setup time

Master

tLEAD

tSPcyc

Slave

—

tPcyc

SSL hold time

Master

tLAG

tSPcyc

Slave

—

tPcyc

Data output delay time

Master

tOD

—18

Slave

—

3 × tPcyc + 40

Data output hold time

Master

tOH

0—

Slave

—

Successive transmission

delay time

Master

tTD

tSPcyc + 2 × tPcyc

8 × tSPcyc

+ 2 × tPcyc

Slave

4 × tPcyc

—

MOSI and MISO rise/

fall time

Output

tDr, tDf

—5

Input

—

μs

SSL rise/fall time

Output

tSSLr,

tSSLf

—5

Input

—

μs

Slave access time

tSA

—4

tPcyc

Figure 5.35 and

Figure 5.36

Slave output release time

tREL

—3

tPcyc

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