R5F5630ECDFB datasheet(138/165 Pages) RENESAS

138 / 165 page

R01DS0060EJ0100 Rev.1.00

Page 138 of 168

Sep 13, 2011

RX630 Group

5. Electrical Characteristics

Note 1. tPcyc: PCLK cycle

Table 5.17

Timing of On-Chip Peripheral Modules (3)

Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0

VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V

PCLK = 8 to 50 MHz

Ta = Topr

High drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit*1

Test Conditions

Simple

SPI

SCK clock cycle output (master)

tSPcyc

65536

tPcyc

Figure 5.32

SCK clock cycle input (slave)

65536

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise/fall time

tSPCKr, tSPCKf

—20

Data input setup time

tSU

—

Figure 5.33 to

Figure 5.36

Data input hold time

—

SS input setup time

tLEAD

1—

tSPcyc

SS input hold time

tLAG

1—

tSPcyc

Data output delay time

tOD

—40

Data output hold time

tOH

—

Data rise/fall time

tDr, tDf

—20

SS input rise/fall time

tSSLr, tSSLf

—20

Save access time

tSA

—5

tPcyc

Figure 5.35 and

Figure 5.36

Slave output release time

tREL

—5

tPcyc

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