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EM351-RTR Datasheet(PDF) 49 Page - List of Unclassifed Manufacturers

Part # EM351-RTR
Description  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  240 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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EM351-RTR Datasheet(HTML) 49 Page - List of Unclassifed Manufacturers

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EM351 / EM357
6-14
120-035X-000D
Preliminary
6.5.5
Registers
PERIPHERAL_DISABLE
Peripheral Disable Register
Address: 0x40004038 Reset: 0x0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
PERIDIS_RSVD
PERIDIS_ADC
PERIDIS_TIM2
PERIDIS_TIM1
PERIDIS_SC1
PERIDIS_SC2
Bitname
Bitfield
Access
Description
PERIDIS_RSVD
[5]
RW
Reserved: this bit can change during normal operation. When writing to
PERIPHERAL_DISABLE, the value of this bit must be preserved.
PERIDIS_ADC
[4]
RW
Disable the clock to the ADC peripheral.
PERIDIS_TIM2
[3]
RW
Disable the clock to the TIM2 peripheral.
PERIDIS_TIM1
[2]
RW
Disable the clock to the TIM1 peripheral.
PERIDIS_SC1
[1]
RW
Disable the clock to the SC1 peripheral.
PERIDIS_SC2
[0]
RW
Disable the clock to the SC2 peripheral.
6.6
Security Accelerator
The EM35x contains a hardware AES encryption engine accessible from the ARM
® CortexTM-M3. NIST-based
CCM, CCM*, CBC-MAC, and CTR modes are implemented in hardware. These modes are described in the IEEE
802.15.4-2003 specification, with the exception of CCM*, which is described in the ZigBee Security Services
Specification 1.0.



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