SA56004GD datasheet(14/36 Pages) NXP

14 / 36 page

SA56004X_5

Product data sheet

Rev. 05 — 22 May 2008

14 of 36

NXP Semiconductors

SA56004X

Digital temperature sensor with overtemperature alarms

Status register, at address 02h, during the interrupt service routine and then reset the

ALERT mask bit 7 in the Conﬁguration register to logic 0 at the end of the interrupt service

routine (see Figure 6).

In order for the SA56004X to respond to the ARA command, the bit D0 in the ALERT

mode register must be set LOW.

ALERT mask bit 7 and the ALERT mode bit D0 are both LOW for the POR default.

The following events summarize the ALERT output interrupt operation in the SMBus Alert

mode:

Event A: Master senses the ALERT line being LOW.

Event A to B: Master sends a read command using the common 7-bit Alert Response

Address (ARA) of 0001100.

Event A to B: Alerting device(s) return ACK signal and their addresses using the

I2C-bus Arbitration (the device with the lowest address value sends its address ﬁrst. The

master can repeat the alert reading process and work up through all the interrupts).

Event B: Upon the successful completion of returning address, the SA56004X resets its

ALERT output (to OFF) and sets the ALERT mask bit 7 in its conﬁguration register.

Event C: Master should read the device status register to identify and correct the

conditions that caused the Alert interruption. The status register is reset.

Event D: Master resets the ALERT mask bit 7 in the conﬁguration register to enable the

device ALERT output interruption.

Remark: The bit assignment of the returned data from the ARA reading is listed in

Table 16. If none of the devices on the bus is alerted then the returned data from ARA

reading will be FFh (1111 1111).

Fig 6.

ALERT pin in SMBus Alert mode

temperature

002aad215

remote temperature high limit

remote diode temperature

ALERT pin

status register bit 4

(RHIGH)

SA56004GD Datasheet(PDF) 14 Page - NXP Semiconductors