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SA56004GD Datasheet(PDF) 23 Page - NXP Semiconductors |
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SA56004GD Datasheet(HTML) 23 Page - NXP Semiconductors |
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23 / 36 page ![]() SA56004X_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 22 May 2008 23 of 36 NXP Semiconductors SA56004X Digital temperature sensor with overtemperature alarms [1] The switching characteristics of the SA56004X fully meet or exceed all parameters specified in SMBus version 2.0. The following parameters specify the timing between the SCLK and SDATA signals in the SA56004X. They adhere to, but are not necessarily specified as the SMBus specifications. [2] Delay from SDATA STOP to SDATA START. [3] Delay from SDATA START to first SCLK HIGH-to-LOW transition. [4] Delay from SCLK HIGH-to-LOW transition to SDATA edges. [5] Delay from SDATA edges to SCLK LOW-to-HIGH transition. [6] Delay from SCLK LOW-to-HIGH transition to restart SDATA. [7] Delay from SCLK HIGH-to-LOW transition to SDATA STOP condition. [8] LOW period for reset of SMBus. Table 19. SMBus interface characteristics VDD = 3.0 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. These specifications are guaranteed by design and not tested in production. Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage SCLK, SDATA; VDD = 2.7 V to 5.5 V 2.2 - - V VIL LOW-level input voltage SCLK, SDATA; VDD = 2.7 V to 5.5 V - - 0.8 V IOL LOW-level output current ALERT, T_CRIT; VOL = 0.4 V 1.0 - - mA SDATA; VOL = 0.6 V 6.0 - - mA IOH LOW-level output current - - 1.0 µA IIL LOW-level input current −1.0 - - µA IIH HIGH-level input current - - 1.0 µA Ci input capacitance SCLK, SDATA - 5 - pF SMBus digital switching characteristics[1] fSCLK SCLK operating frequency - - 400 kHz tLOW SCLK LOW time 10 % to 10 % 600 5000 - ns tHIGH SCLK HIGH time 90 % to 90 % 600 5000 - ns tBUF SMBus free time[2] 600 - - ns tHD;STA hold time of START condition[3] 10 % of SDATA to 90 % of SCLK 600 - - ns tHD;DAT hold time of data[4] 0 300 - ns tSU;DAT set-up time of data in[5] 250 - - ns tSU;STA set-up time of repeat START condition[6] 90 % to 90 % 250 - - ns tSU;STO set-up time of STOP condition[7] 90 % of SCLK to 90 % of SDATA 250 - - ns tr rise time SCLK and SDATA - - 1 µs tf fall time SCLK and SDATA - - 300 ns tof output fall time CL = 400 pF; IO = 3 mA - - 250 ns tto(SMBus) SMBus time-out time[8] 25 - 35 ms |
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