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PCF8563 Datasheet(PDF) 12 Page - NXP Semiconductors |
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PCF8563 Datasheet(HTML) 12 Page - NXP Semiconductors |
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12 / 32 page  PCF8563_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 21 February 2008 12 of 32 NXP Semiconductors PCF8563 Real-time clock/calendar Operation example: 1. Set EXT_CLK test mode (control_status_1, bit TEST1 = 1) 2. Set STOP (control_status_1, bit STOP = 1) 3. Clear STOP (control_status_1, bit STOP = 0) 4. Set time registers to desired value 5. Apply 32 clock pulses to CLKOUT 6. Read time registers to see the first change 7. Apply 64 clock pulses to CLKOUT 8. Read time registers to see the second change Repeat steps 7 and 8 for additional increments. 7.8 Power-On Reset (POR) override The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of this mode requires that the I2C-bus pins, SDA and SCL, be toggled in a specific order as shown in Figure 8. All timings are required minimums. Once the Override mode has been entered, the device immediately stops being reset and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus access. The Override mode may be cleared by writing a logic 0 to TESTC. TESTC must be set to logic 1 before re-entry into the Override mode is possible. Setting TESTC to logic 0 during normal operation has no effect except to prevent entry into the POR override mode. Table 25 shows the register reset values. Fig 8. POR override sequence mgm664 SCL 500 ns 2000 ns SDA 8 ms override active power up Table 25. Register reset value[1] Address Register name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h control_status_1 0 0 0 0 1 0 0 0 01h control_status_2 x x 0 0 0 0 0 0 02h VL_seconds 1 x x x x x x x 03h minutes 1 x x x x x x x 04h hours x x x x x x x x |
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