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PCF8563 Datasheet(PDF) 10 Page - NXP Semiconductors |
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PCF8563 Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 32 page  PCF8563_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 21 February 2008 10 of 32 NXP Semiconductors PCF8563 Real-time clock/calendar 7.6.5 Clock output control register 7.6.6 Countdown timer The timer register is an 8-bit binary countdown timer. It is enabled and disabled via the timer control register bit TE. The source clock for the timer is also selected by the timer control register. Other timer properties such as interrupt generation are controlled via control_status_2 register. For accurate read back of the countdown value, the I2C-bus clock (SCL) must be operating at a frequency of at least twice the selected timer clock. Table 18. Day_alarm - Day alarm register (address 0Bh) bit description Bit Symbol Value Description 7 AE 0 day alarm is enabled 1 day alarm is disabled 6 x not relevant 5 to 0 ALARM_DAYS[5:0] 01 to 31 the day alarm information, coded in BCD format Table 19. Weekday_alarm - Weekday alarm register (address 0Ch) bit description Bit Symbol Value Description 7 AE 0 weekday alarm is enabled 1 weekday alarm is disabled 6 to 3 x not relevant 2 to 0 ALARM_ WEEKDAYS[2:0] 0 to 6 the weekday alarm information, coded in BCD format Table 20. CLKOUT_control - CLKOUT control register (address 0Dh) bit description Bit Symbol Value Description 7 FE 0 the CLKOUT output is inhibited and set to high-impedance 1 the CLKOUT output is activated 6 to 2 x not relevant 1 to 0 FD[1:0] see Table 21 these bits control the frequency output at pin CLKOUT Table 21. FD1 and FD0: CLKOUT frequency selection FD1 FD0 CLKOUT frequency 0 0 32.768 kHz 0 1 1024 Hz 1 0 32 Hz 11 1 Hz |
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Similar Description - PCF8563 |
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