PCF8563 datasheet(20/32 Pages) NXP

Part #	PCF8563

Description	Real-time clock/calendar

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Manufacturer	NXP [NXP Semiconductors]

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20 / 32 page

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

20 of 32

NXP Semiconductors

PCF8563

Real-time clock/calendar

11. Dynamic characteristics

[1]

Unspeciﬁed for fCLKOUT = 32.768 kHz.

[2]

All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage

swing of VSS to VDD.

[3]

A detailed description of the I2C-bus speciﬁcation, with applications, is given in brochure

The I2C-bus speciﬁcation. This brochure may

be ordered using the code 9398 393 40011.

[4]

I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

Table 28.

Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs =40kΩ; CL = 8 pF; unless otherwise

speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Oscillator

CL(itg)

integrated load capacitance

15

25

35

pF

∆fosc/fosc

relative oscillator frequency variation

∆V

DD = 200 mV;

Tamb =25 °C

-2

× 10−7 -

Quartz crystal parameters (f = 32.768 kHz)

Rs

series resistance

-

40

k

Ω

CL

load capacitance

parallel

-

10

-

pF

Ctrim

trimmer capacitance

5

-

25

pF

CLKOUT output

δCLKOUT

duty cycle on pin CLKOUT

[1] -50

-

%

I2C-bus timing characteristics (see Figure 21)

[2][3]

fSCL

SCL clock frequency

[4] -

-

400

kHz

tHD;STA

hold time (repeated) START condition

0.6

-

µs

tSU;STA

set-up time for a repeated START condition

0.6

-

µs

tLOW

LOW period of the SCL clock

1.3

-

µs

tHIGH

HIGH period of the SCL clock

0.6

-

µs

tr

rise time of both SDA and SCL signals

SDA

-

0.3

µs

SCL

-

0.3

µs

tf

fall time of both SDA and SCL signals

SDA

-

0.3

µs

SCL

-

0.3

µs

Cb

capacitive load for each bus line

-

400

pF

tSU;DAT

data set-up time

100

-

ns

tHD;DAT

data hold time

0

-

ns

tSU;STO

set-up time for STOP condition

0.6

-

µs

tw(spike)

spike pulse width

on bus

-

50

ns

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