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MPC8544ECVTALF Datasheet(PDF) 61 Page - Freescale Semiconductor, Inc |
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MPC8544ECVTALF Datasheet(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 120 page ![]() MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 61 I 2C Figure 38 provides the AC test load for the I2C. Figure 38. I2C AC Test Load Figure 39 shows the AC timing diagram for the I2C bus. Figure 39. I2C Bus AC Timing Diagram Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.2 × OVDD —V — Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I 2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I 2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I 2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. The MPC8544E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF. Table 52. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 51). Parameter Symbol1 Min Max Unit Notes Output Z0 = 50 Ω OVDD/2 RL = 50 Ω Sr S SDA SCL tI2CF tI2SXKL tI2CL tI2CH tI2DXKL,tI2OXKL tI2DVKH tI2SXKL tI2SVKH tI2KHKL tI2PVKH tI2CR tI2CF PS |
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