R8CSLASH13 datasheet(191/224 Pages) RENESAS

191 / 224 page

R8C/13 Group

Rev.1.20

Jan 27, 2006

page 180 of 205

REJ09B0111-0120

17.4.5 Full Status Check

When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur-

rence of each specific error. Therefore, execution results can be verified by checking these status bits

(full status check). Table 17.6 lists errors and FMR0 register status. Figure 17.12 shows a full status

check flowchart and the action to be taken when each error occurs.

Table 17.6 Errors and FMR0 Register Status

FRM00 register

(status register)

status

Error

Error occurrence condition

FMR07

FMR06

(SR5)

(SR4)

Command

• When any command is not written correctly

sequence error • When invalid data was written other than those that can be writ-

ten in the second bus cycle of the Block Erase command (i.e.,

other than ‘D016’ or ‘FF16’)(1)

•When executing the program command or block erase command

while rewriting is disabled using the FMR02 bit in the FMR0 regis-

ter, the FMR15 or FMR16 bit in the FMR1 register.

• When inputting and erasing the address in which the Flash

memory is not allocated during the erase command input.

• When executing to erase the block which disables rewriting dur-

ing the erase command input.

• When inputting and writing the address in which the Flash

memory is not allocated during the write command input.

• When executing to write the block which disables rewriting during

the write command input.

Erase error

• When the Block Erase command was executed but not automati-

cally erased correctly

Program error

• When the Program command was executed but not automatically

programmed correctly.

17.4 CPU Rewrite Mode

NOTES:

1. Writing ‘FF16’ in the second bus cycle of these commands places the microcomputer in read array

mode, and the command code written in the first bus cycle is nullified.

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