R8CSLASH13 datasheet(190/224 Pages) RENESAS

190 / 224 page

R8C/13 Group

Rev.1.20

Jan 27, 2006

page 179 of 205

REJ09B0111-0120

17.4.4 Status Register

The status register indicates the operating status of the flash memory and whether an erase or pro-

gramming operation terminated normally or in error. The status of the status register can be known by

reading the FMR00, FMR06, and FMR07 bits in the FMR0 register.

Table 17.5 lists the status register.

In EW0 mode, the status register can be read in the following cases:

(1) When a given address in the user ROM area is read after writing the Read Status Register com-

mand

(2) When a given address in the user ROM area is read after executing the Program or Block Erase

command but before executing the Read Array command.

• Sequence Status (SR7 and FMR00 Bits )

The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto

programming and auto erase, and is set to “1” (ready) at the same time the operation finishes.

• Erase Status (SR5 and FMR07 Bits)

Refer to Section 17.4.5, “Full Status Check.”

• Program Status (SR4 and FMR06 Bits)

Refer to Section 17.4.5, “Full Status Check.”

Table 17.5 Status Register

Status

bit

SR4 (D4)

SR5 (D5)

SR7 (D7)

SR6 (D6)

Status name

Contents

SR1 (D1)

SR2 (D2)

SR3 (D3)

SR0 (D0)

Program status

Erase status

Sequencer status

Reserved

"1"

Ready

Terminated in error

"0"

Busy

Terminated normally

Reserved

FMR0

bit

FMR00

FMR07

FMR06

Value

after

reset

• D7 to D0: Indicates the data bus which is read out when the Read Status Register command is executed.

• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the Clear Status Register com-

mand.

• When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program and Block Erase commands are not

accepted.

17.4 CPU Rewrite Mode

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