R8CSLASH20 datasheet(125/501 Pages) RENESAS

125 / 501 page

R8C/20 Group, R8C/21 Group

12. Interrupts

Rev.2.00 Aug 27, 2008

Page 109 of 458

REJ09B0250-0200

Controlling an interrupt with the I flag, IR bit, ILVL0 to ILVL2 bits and IPL by Timer RD (channel 0), Timer RD

(channel 1), clock synchronous serial I/O with chip select and I2C bus interface is the same as that by other

maskable interrupts. However, since an interrupt source is generated based on multiple interrupt request sources,

there are the following differences from other maskable interrupts:

• When bits in the enable register corresponding to set bits in the status register to 1 are set to 1 (enable

interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested).

• When either bits in the status register or bits in the enable register corresponding to bits in the status register, or

both of them are set to 0, the IR bit is set to 0 (interrupt not requested). Basically, even though the interrupt is

not acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. Also, the IR bit is not

set to 0 although 0 is written to the IR bit.

• Since each bit in the status register is not automatically set to 0 even if the interrupt is acknowledged.

Therefore, the IR bit is not also automatically set to 0 when the interrupt is acknowledged. Set each bit in the

status register to 0 in the interrupt routine. Refer to the status register figure how to set each bit in the status

• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is

set to 1, the IR bit remains 1.

• When multiple bits in the enable register are set to 1, determine by the status register which request source

causes an interrupt.

Refer to chapters of each peripheral function (14.3 Timer RD, 16.2 Clock Synchronous Serial I/O with Chip

Select (SSU) and 16.3 I2C Bus Interface) for the status register and enable register.

Refer to 12.1.6 Interrupt Control for the interrupt control register.

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