R8CSLASH20 datasheet(124/501 Pages) RENESAS

124 / 501 page

R8C/20 Group, R8C/21 Group

12. Interrupts

Rev.2.00 Aug 27, 2008

Page 108 of 458

REJ09B0250-0200

12.5

Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts

and I2C bus Interface Interrupts (Interrupts with Multiple Interrupt Request

Sources)

Timer RD (channel 0), timer RD (channel 1), clock synchronous serial I/O with chip select and I2C bus interface

have several interrupt request sources and an interrupt request is generated by the logical OR of several interrupt

request sources and the logical OR is reflected in the IR bit in the interrupt control register. Therefore, these

peripheral functions which have the status register of its own interrupt request sources (status register) and the

enable register of the interrupt request sources (enable register) control the generations of the interrupt request

(change of the IR bit in the interrupt control register). Table 12.8 lists the Registers Associated with Timer RD

Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and I2C bus Interface Interrupt and Figure

12.19 shows the Block Diagram of Timer RD Interrupt.

Figure 12.19

Block Diagram of Timer RD Interrupt

Table 12.8

Registers Associated with Timer RD Interrupt, Clock Synchronous Serial I/O with

Chip Select Interrupt, and I2C bus Interface Interrupt

Status Register of

Interrupt Request Source

Enable Register of

Interrupt Request Source

Interrupt Control

Timer RD

Channel 0

TRDSR0

TRDIER0

TRD0IC

Channel 1

TRDSR1

TRDIER1

TRD1IC

Clock Synchronous

Serial I/O with Chip

Select

SSSR

SSER

SSUIC

I2C Bus Interface

ICSR

ICIER

IICIC

Timer RD (channel i)

Interrupt request

(IR bit in TRDiIC register)

IMFA bit

IMIEA bit

IMFB bit

IMIEB bit

IMFC bit

IMIEC bit

IMFD bit

IMIED bit

UDF bit

OVF bit

OVIE bit

i = 0 or 1

IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register

IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register

Channel i

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