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STA320 Datasheet(PDF) 5 Page - STMicroelectronics |
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STA320 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 37 page ![]() 5/37 STA320 4.1.3 Stop Condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA320 and the bus master. 4.1.4 Data Input During the data input the STA320 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. 4.2 DEVICE ADDRESSING To start communication between the master and the STA320, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA320 the I2C interface has two device addresses depending on the SA port configuration, 0x34 when SA = 0, and 0x36 when SA = 1. The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode and 0 for write mode. After a START condition the STA320 identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address. 4.3 WRITE OPERATION Following the START condition the master sends a device select code with the RW bit set to 0. The STA320 acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA320 again responds with an acknowledgement. 4.3.1 Byte Write In the byte write mode the master sends one data byte, this is acknowledged by the STa320. The master then terminates the transfer by generating a STOP condition. 4.3.2 Multi-byte Write The multi-byte write modes can start from any internal address. The master generating a STOP condition ter- minates the transfer. Figure 3. Write Mode Sequence DEV-ADDR ACK START RW SUB-ADDR ACK DATA IN ACK STOP BYTE WRITE DEV-ADDR ACK START RW SUB-ADDR ACK DATA IN ACK STOP MULTIBYTE WRITE DATA IN ACK |
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