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STA320

5.1 Configuration Register A (address 00h)

5.1.1 Master Clock Select

The STA320 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, 96kHz, Therefore the internal clock

will be:

– 32.768Mhz for 32kHz

– 45.1584Mhz for 44.1khz, 88.2kHz and 176.4kHz

– 49.152Mhz for 48kHz, 96kHz, and 192kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency(fs). The

relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (Input

Rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit deter-

mine the oversampling ratio used internally.

Addr

Name

D7

D6

D5

D4

D3

D2

D1

D0

0x1C

B2cf3

C2B7

C2B6

C2B5

C2B4

C2B3

C2B2

C2B1

C2B0

0x1D

A1cf1

C3B23

C3B22

C3B21

C3B20

C3B19

C3B18

C3B17

C3B16

0x1E

A1cf2

C3B15

C3B14

C3B13

C3B12

C3B11

C3B10

C3B9

C3B8

0x1F

A1cf3

C3B7

C3B6

C3B5

C3B4

C3B3

C3B2

C3B1

C3B0

0x20

A2cf1

C4B23

C4B22

C4B21

C4B20

C4B19

C4B18

C4B17

C4B16

0x21

A2cf2

C4B15

C4B14

C4B13

C4B12

C4B11

C4B10

C4B9

C4B8

0x22

A2cf3

C4B7

C4B6

C4B5

C4B4

C4B3

C4B2

C4B1

C4B0

0x23

B0cf1

C5B23

C5B22

C5B21

C5B20

C5B19

C5B18

C5B17

C5B16

0x24

B0cf2

C5B15

C5B14

C5B13

C5B12

C5B11

C5B10

C5B9

C5B8

0x25

B0cf3

C5B7

C5B6

C5B5

C5B4

C5B3

C5B2

C5B1

C5B0

0x26

Cfud

RA

R1

WA

W1

0x27

MPCC1

MPCC15

MPCC14

MPCC13

MPCC12

MPCC11

MPCC10

MPCC9

MPCC8

0x28

MPCC2

MPCC7

MPCC6

MPCC5

MPCC4

MPCC3

MPCC2

MPCC1

MPCC0

0x29

DCC1

DCC15

DCC14

DCC13

DCC12

DCC11

DCC10

DCC9

DCC8

0x2A

DCC2

DCC7

DCC6

DCC5

DCC4

DCC3

DCC2

DCC1

DCC0

0x2B

FDRC1

FDRC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

0x2C

FDRC2

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

0x2D

Status

PLLUL

OCWARN TFAULT

FAULT

TWARN

0x2E

BC0

RESRES

RESRES

RESRES

RES

RES

0x2F

BS0

RESRES

RESRES

RESRES

BS9

BS8

0x30

BS1

RESRES

RESRES

RESRES

RES

RES

0x31

B1

RESRES

RESRES

RESRES

RES

RES

0x32

B2

RESRES

RESRES

RESRES

RES

RES

0x33

T

RESRES

RESRES

RESRES

RES

RES

D7

D6

D5

D4

D3

D2

D1

D0

FDRB

TWAB

TFRB

IR1

IR0

MCS2

MCS1

MCS0

0

1

1

000

11

BIT

R/W

RST

NAME

DESCRIPTION

0

R/W

1

MCS0

Master Clock Select : Selects the ratio between the input

1R/W

1

MCS1

2R/W

0

MCS2

Table 8. Register Summary (continued)