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STA320

5.2.4 Channel Input Mapping

Mapping registers. This allows for flexibility in processing. The default settings of these registers map each

5.3 Configuration Register C(Address 02h)

5.3.1 DDX Power Output Mode

The DDX Power Output Mode selects how the DDX output timing is configured. Different power devices use

different output modes. The STA50x or STA51x recommended use is OM = 10.

Table 13. Output Modes

5.3.2 DDX Compensating Pulse Size Register

Table 14. Compensating Pulse Size

BIT

R/W

RST

NAME

DESCRIPTION

6R/W

0

C1IM

7R/W

1

C2IM

D7

D6

D5

D4

D3

D2

D1

D0

OCRB

CSZ4

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

1

10000

1

0

BIT

R/W

RST

NAME

DESCRIPTION

0

R/W

0

OM0

DDX Power Output Mode: Selects configuration of DDX

output.

1R/W

1

OM1

OM(1,0)

Output Stage – Mode

00

STA50x/STA51x – Drop Compensation

01

Discrete Output Stage – Tapered Compensation

10

STA50x/STA51x – Full Power Mode

11

Variable Drop Compensation (CSZx bits)

BIT

R/W

RST

NAME

DESCRIPTION

2

R/W

0

CSZ0

Contra Size Register: When OM(1,0) = 11, this register

determines the size of the DDX compensating pulse from 0

clock ticks to 31 clock periods.

3R/W

0

CSZ1

4R/W

0

CSZ2

5R/W

0

CSZ3

6R/W

1

CSZ4

CSZ(4..0)

Compensating Pulse Size

00000

0ns(0 tick) Compensating Pulse Size

00001

10ns(1 tick) Clock period Compensating Pulse Size

……

11111

310ns(31 tick) Clock period Compensating Pulse Size