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5.6.6 IC Power Down

The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output

will begin a soft-mute.

After the mute condition is reached, EAPD will be asserted to power down the power-stage, then the mas-

consumption stateConf

5.6.7 External Amplifier Power Down

5.7 Volume Control Registers(Addresses 06-0Ah)

5.7.1 Mute/QXpander RegisterI

5.7.2 Thermal Fault(TWARN2) Recovery Bypass

The TWARN2(Thermal Fault) input is used to indicate a thermal fault condition by an appropriate power

device. When TWARN2 is asserted (set to 0), the power control block will attempt a recovery from the

fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery),

hold it at 0 for period of time in the range of .1ms to 1 second as defined by the Fault-Detect Recovery

Constant register (FDRC registers 29-2Ah), then toggle it back to 1.

This sequence is repeated as log as the fault indication exists. This feature is disabled by default but can

be enabled by setting the TFRB control bit to 0.

5.7.3 Qxpander Enable

5.7.4 Qfilter Select

BIT

R/W

RST

NAME

DESCRIPTION

7

R/W

1

PWDN

IC Power Down:

0 - IC Power Down Low-Power Condition

1 - IC Normal Operation

BIT

R/W

RST

NAME

DESCRIPTION

7

R/W

0

EAPD

External Amplifier Power Down:

0 -External Power Stage Power Down Active

1 -Normal Operation

D7

D6

D5

D4

D3

D2

D1

D0

QFILT

QXEN

TFRB

C3M

C2M

C1M

MMUTE

00

100

0

00

BIT

R/W

RST

NAME

DESCRIPTION

4

R/W

1

TFRB

Thermal-Fault (TWARN2) Recovery Bypass:

0 - Thermal fault recovery enabled

1 - Thermal fault recovery disabled

BIT

R/W

RST

NAME

DESCRIPTION

6

R/W

0

QXEN

Qxpander Enable:

0 - QXPander Disabled

1 - QXPander Enabled with proper security code

BIT

R/W

RST

NAME

DESCRIPTION

7

R/W

0

QFilt

Qfilter Select

0 - Qfilter Used

1 - Simple LPF Used