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STA320 Datasheet(PDF) 15 Page - STMicroelectronics |
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STA320 Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 37 page  15/37 STA320 5.6.1 Output Configuration Table 15. Output Configuration Engine Selection 5.6.2 Invalid Input Detect Mute Enable Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the sig- nals are perceived as invalid. 5.6.3 Detects loss of input MCLK in binary mode and will output 50% duty cycle. 5.6.4 Actively prevents double trigger of LRCLK. 5.6.5 When active will issue a power device power down signal(EAPD) on clock loss detection BIT R/W RST NAME DESCRIPTION 0 R/W 0 OCFG0 Selects the Output Configuration 1R/W 0 OCFG1 OCFG(1..0) Output Configuration 00 2 Channel (Full-Bridge) Power, 1 Channel DDX: 1A/1B → 1A/1B w/ C1BO 0° 2A/2B → 2A/2B w/ C2BO 90/180° 3A/3B →3A/3B w/ C3BO 45° 01 2(Half-Bridge).1(Full-Bridge) On-Board Power: 1A → 1A Binary 0° 2A → 1B Binary 90° 3A/3B → 2A/2B Binary 45° 1A → 3A Binary 0° 2A → 3B Binary 90° 10 2 Channel (Full-Bridge) Power, 2 Channel Data-Out: 1A/1B → 1A/1B Binary 0° 2A/2B → 2A/2B Binary 90° 1A → 3A Binary 0° 2A → 3B Binary 90° 11 1 Channel Mono-Parallel: 3A → 1A/1B w/ C3BO 45° 3B → 2A/2B w/ C3BO 45° 3A/3B → 3A/3B w/ C3BO 45° Note To the left of the arrow is the processing channel. Note that though the defaults are shown, using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs BIT R/W RST NAME DESCRIPTION 2 R/W 1 IDE Invalid Input Detect Mute Enable: Setting of 1 enables the automatic invalid input detect mute BIT R/W RST NAME DESCRIPTION 3 R/W 1 BCLE Binary Output Mode Clock Loss Detection Enable BIT R/W RST NAME DESCRIPTION 4 R/W 1 LDTE LRCLK Double Trigger Protection Enable BIT R/W RST NAME DESCRIPTION 5 R/W 0 ECLE Auto EAPD on Clock Loss |
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