LT8708 datasheet(45/48 Pages) AD

45 / 48 page

LTC7871

Rev. 0

For more information www.analog.com

PSYNC =

48V –12V

48V

•15A2

• (1

+0.005• 75°C–25°C

(

))•5.2mΩ

[

]

⎧

⎨

⎪

⎩

⎪

⎫

⎬

⎪

⎭

⎪

•2

= 1.1W

{

}•2

= 2.2W

CHIGH is chosen for an equivalent RMS current rating of

at least 20A. CLOW is chosen with an equivalent ESR of

10mΩ for low output ripple. The VLOW output ripple in

continuous mode will be highest at the maximum VHIGH

voltage. The VLOW output voltage ripple due to ESR

is approximately:

VLOWRIPPLE = RESR • ∆IL = 0.01Ω • 8.8A = 88mV

Further reductions in VLOW output voltage ripple can be

made by placing ceramic capacitors across CLOW.

If the output load is a battery, the voltage loop is first set

for the desired output voltage and then the charge current

can be regulated using the current regulation loop—via

the SETCUR and IMON pins. Selecting a maximum charge

current of 120A, the desired SETCUR pin voltage is cal-

culated using:

VSETCUR =

K •IL MAX

(

) •RSENSE

20 •120A •1m

= 400mV

The SETCUR pin can be driven by an ADC’s output to

400mV for the best accuracy. If one is not available, the

16μA current sourced out of the SETCUR pin can be used

to set the voltage with a resistor from SETCUR to ground,

calculated using:

RSETCUR =

400mV

16µA

= 25k

A 1% or more accurate 30.1k resistor can be chosen to

allow some design margin. The 16μA current out of the

SETCUR pin can be programmed by the SPI interface so

the maximum charge current can be changed on-the-fly.

Typically, C1 is selected in the range of 0.047μF to 0.47μF.

If C1 is chosen to be 0.1μF, R1 and R2 will be 16.9kΩ

and 1.69kΩ respectively. The bias current at SNSD+ and

SNSA+ is about 50nA, and it causes some small error to

the current sense signal. If C2 is also chosen to be 0.1μF,

R3 will be 1.5kΩ.

Figure 17.

LTC7871

7871 F17

16.9k

0.1µF

SNSD+

SNS–

SNSA+

1.5k

6.8µH

0.1µF

VLOW

1.69k

RSENSE Resistor Sensing in Design Example

The power dissipation on the top MOSFET can be eas-

ily estimated. Set the gate drive voltage (DRVCC) to be

10V. Choosing two Infineon BSC117N08NS5 MOSFETs

results in:

RDS(ON) = 11.7mΩ (max),

VMILLER = 5V, CMILLER ≅ 19pF.

At typical VHIGH voltage with TJ (estimated) = 75°C:

PMAIN =

12V

48V

•15A2

• (1

+0.005• 75°C–25°C

(

))•11.7mΩ

[

]

+48V2 •

15A

• 4

Ω•19pF

•

−5

⎛

⎝⎜

⎞

⎠⎟ •150k

⎧

⎨

⎪

⎪⎪

⎩

⎪

⎫

⎬

⎪

⎪⎪

⎭

⎪

•2

= 823mW+79mW

{

}•2

= 1804mW

Two Infineon BSC052N08NS5 MOSFETs, RDS(ON) =

5.2mΩ, COSS = 370pF are chosen for the bottom MOSFET.

The resulting power loss is:

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