IS25LP256D-RLLA3 datasheet(138/174 Pages) ISSI

138 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

138

Rev A6

04/15/2019

8.48 WRITE BANK ADDRESS REGISTER OPERATION (WRBRNV: 18h, WRBRV: 17h/C5h)

The Write Bank Address Register (WRBRNV and WRBRV) instruction is used to write address bits above A23, into

the Bank Address Register (BAR). WRBRNV is used to write the non-volatile Bank Address Register and WRBRV

is used to write the volatile Bank Address Register. The instruction is also used to write the Extended Address

Control bit (EXTADD) that is also in BAR[7]. BAR provides the high order addresses needed by devices having

more than 128Mbits (16Mbytes), when using 3-byte address commands without extended addressing enabled

(BAR[7] EXTADD = 0).

WRBRNV requires the Write Enable (WREN) command to precede it while WRBRV does not require WREN

command.

The WRBRNV/WRBRV instruction is followed by the data byte. The Bank Address Register is one data byte in

length. The Write In Progress (WIP) bit

is “1” during WRBRNV operation, and is “0” when it is completed. The

WRBRV command has no effect on the Write In Progress (WIP) bit. Any bank address bit reserved for the future

should always be written as “0”. Data is shifted in from SI and in SPI whereas data is shifted in via four pins (IO0-

IO3) in QPI.

Note: When WRBRNV is executed, the volatile Bank Address Register is set as well as the non-volatile Bank Address

Figure 8.110 Write Bank Address Register Sequence In SPI Mode

Instruction = 18h or 17h/C5h

CE #

SCK

Data In

Mode 3

Mode 0

High Impedence

Figure 8.111 Write Bank Address Register Sequence In QPI Mode

18h or

17h/C5h

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data In

IS25LP256D-RLLA3 Datasheet(PDF) 138 Page - Integrated Silicon Solution, Inc