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IS25LP256D-RLLA3 Datasheet(PDF) 136 Page - Integrated Silicon Solution, Inc

Part # IS25LP256D-RLLA3
Description  SERIAL FLASH MEMORY WITH 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  174 Pages
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP256D-RLLA3 Datasheet(HTML) 136 Page - Integrated Silicon Solution, Inc

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IS25LP256D
IS25WP256D
Integrated Silicon Solution, Inc.- www.issi.com
136
Rev A6
04/15/2019
AUTOBOOT REGISTER WRITE OPERATION (WRABR, 15h)
Before the WRABR command can be accepted, a Write Enable (WREN) command must be issued and decoded
by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The WRABR command is entered by shifting the instruction and the data bytes, least significant byte first, most
significant bit of each byte first. The WRABR data is 32bits in length.
CE# must be driven high after the 32nd bit of data has been latched. If not, the WRABR command is not executed.
As soon as CE# is driven high, the WRABR operation is initiated. While the WRABR operation is in progress, Status
Register or Extended Read Register may be read to check the value of the Write In Progress (WIP) bit. The WIP
bit is “1” during the WRABR operation, and is “0” when it is completed. When the WRABR cycle is completed, the
WEL is set to “0”.
Figure 8.106 WRABR Sequence In SPI Mode
Instruction = 15h
7
CE #
SCK
SI
3
2
SO
1
0
Data In 1
6
5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
4
High Impedance
...
...
Figure 8.107 WRABR Sequence In QPI Mode
15h
0
1
Mode 3
Mode 0
2
3
7:4
3:0
CE#
SCK
IO[3:0]
Data In 1
...
...



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