IS25LP256D-RLLA3 datasheet(137/174 Pages) ISSI

Part #	IS25LP256D-RLLA3

Description	SERIAL FLASH MEMORY WITH 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PDF	174 Pages

Scroll/Zoom	100%

Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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137 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

137

Rev A6

04/15/2019

8.47 READ BANK ADDRESS REGISTER OPERATION (RDBR: 16h/C8h)

The Read Bank Address Register (RDBR) instruction allows the Bank Address Register contents to be read. RDBR

is used to read only a volatile Bank Address Register.

The instruction code is first shifted in. Then the 8-bit Bank Register is shifted out. It is possible to read the Bank

Address Register continuously by providing multiples of eight bits. The maximum operating clock frequency for the

RDBR command is the same with Fast Read Operation.

Data is shifted in from SI and data is shifted out from SO in SPI sequence whereas data in and out is via four pins

(IO0-IO3) in QPI sequence.

Figure 8.108 Read Bank Address Register Sequence In SPI Mode

Instruction = 16h/C8h

CE #

SCK

Data Out

Mode 3

Mode 0

Figure 8.109 Read Bank Address Register Sequence In QPI Mode

16h/C8h

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data Out

IS25LP256D-RLLA3 Datasheet(PDF) 137 Page - Integrated Silicon Solution, Inc