TNETX15AE datasheet(66/78 Pages) TI

66 / 78 page

TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements (see Figure 19)

external SRAM write cycle

NO.

MIN

MAX

UNIT

tc(W)

Cycle time, write

operating characteristics over recommended operating conditions(see Figure 19)

external SRAM write cycle

NO.

PARAMETER

MIN

MAX

UNIT

td(EA)1

Delay time, from OSCIN

↑ to EA20–EA0 valid

td(EWE)1

Delay time, from OSCIN

↓ to EWE↓

td(ED)1

Delay time, from OSCIN

↓ to ED15–ED0 valid

td(EWE)2

Delay time, from OSCIN

↑ to EWE↑

td(ED)2

Delay time, from EWE

↑ to ED15–ED0 invalid

td(EA)2

Delay time, from EWE

↑ to EA20–EA0 invalid

td(ED)3

Delay time, from OSCIN

↑ to ED15–ED0 invalid

EA20–EA0

(Output)

EWE

(Output)

EOE

(Output)

ED15–ED0

(Output)

OSCIN

(Input)

Valid

Figure 19. External SRAM Write Cycle

TNETX15AE Datasheet(PDF) 66 Page - Texas Instruments

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