LP3907TL-JSXSSLASHNOPB datasheet(9/58 Pages) TI1

9 / 58 page

LP3907

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SNVS511S – JUNE 2007 – REVISED APRIL 2016

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Buck Converters SW1, SW2 (continued)

Unless otherwise noted, VIN = 3.6 V, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2-µH ceramic, and TJ = 25°C.

(1)(2)(3)(4)(5)(6)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(8)

The IQ can be defined as the standing current of the LP3907 when the I

2C bus is active and all other power blocks have been disabled

via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the device is powered using a battery.

IPEAK

Buck1 peak switching current limit

1.5

Buck2 peak switching current limit

(8)

Quiescent current “on”

No load PFM mode

µA

RDSON (P)

Pin-pin resistance PFET

200

Ω

RDSON (N)

Pin-pin resistance NFET

180

Ω

TON

Turnon time

Start up from shutdown

500

µs

CIN

Input capacitor

Capacitance for stability

µF

COUT

Output capacitor

Capacitance for stability

µF

(1)

This specification is ensured by design.

7.8

I/O Electrical Characteristics

Unless otherwise noted: Limits apply over the entire junction temperature range for operation, TJ = −40°C to +125°C.

(1)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

VIL

Input low level

0.4

VIH

Input high level

1.2

7.9

Power-On Reset (POR) Threshold/Function

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

nPOR

nPOR = Power on reset forBuck1 and

Buck2

Default

nPOR

threshold

Percentage of target voltage Buck1

or Buck2

VBUCK1 AND VBUCK2 rising

94%

VBUCK1 OR VBUCK2 falling

85%

VOL

Output level low

Load = IoL = 500 mA

0.23

0.5

(1)

This specification is ensured by design.

7.10

2C Interface Timing Requirements

Unless otherwise noted, VIN = 3.6 V and TJ = 25°C.

(1)

MIN

NOM

MAX

UNIT

ƒCLK

Clock frequency

400

kHz

tBF

Bus-free time between start and stop

See(1)

1.3

µs

tHOLD

Hold time repeated start condition

0.6

µs

tCLKLP

CLK low period

1.3

µs

tCLKHP

CLK high period

0.6

µs

tSU

Set-up time repeated start condition

0.6

µs

tDATAHLD

Data hold time

µs

tDATASU

Data set-up time

100

TSU

Set-up time for start condition

0.6

µs

TTRANS

Maximum pulse width of spikes that

must be suppressed by the input filter

of both DATA & CLK signals

LP3907TL-JSXS/NOPB Datasheet(PDF) 9 Page - Texas Instruments

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