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LP3907TL-JSXS/NOPB Datasheet(PDF) 29 Page - Texas Instruments |
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LP3907TL-JSXS/NOPB Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 58 page ![]() 29 LP3907 www.ti.com SNVS511S – JUNE 2007 – REVISED APRIL 2016 Product Folder Links: LP3907 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Programming (continued) 8.5.2 Factory Programmable Options Table 7 shows options EPROM programmed during final test of the LP3907. The system designer that needs specific options is advised to contact the TI sales office. Table 7. Factory-Programmable Options FACTORY PROGRAMMABLE OPTIONS CURRENT VALUE Enable delay for power on code 010 (see Control 1 Register (SCR1) 0x07) SW1 ramp speed 8 mV/µs SW2 ramp speed 8 mV/µs The I2C Chip ID address is offered as a metal mask option. The current address for the WQFN chip equals 0x60, while the address for the DSBGA chip is 0x61. |
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