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LP3907TL-JSXS/NOPB Datasheet(PDF) 28 Page - Texas Instruments |
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LP3907TL-JSXS/NOPB Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 58 page  ack from slave w ack start msb Chip Address lsb msb Register Add lsb msb DATA lsb ack ack stop ack from slave ack from slave SCL start id = K¶60 w ack register addr = K¶10 GDWD DGGU K¶6A ack ack stop SDA rs msb Chip Address lsb r ack repeated start data from slave ack from master r id = K¶60 ack rs . SCL SDA start id = K¶60 w ack addr = K¶02 DGGUHVV K¶$$ GDWD ack ack stop ack from slave w ack start msb Chip Address lsb msb Register Add lsb msb DATA lsb ack ack stop ack from slave ack from slave 1 2 3 4 5 6 7 8 9 1 2 3 ... ADR6 bit7 MSB ADR5 bit6 ADR4 bit5 ADR3 I 2C SLAVE address (chip address) ADR2 bit3 ADR1 bit2 ADR0 bit1 R/W bit0 LSB 1 1 0 0 0 0 0 bit4 28 LP3907 SNVS511S – JUNE 2007 – REVISED APRIL 2016 www.ti.com Product Folder Links: LP3907 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Programming (continued) NOTE According to industry I2C standards for 7-bit addresses, the MSB of an 8-bit address is removed, and communication actually starts with the 7th most significant bit. For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. The LP3907 has factory-programmed I2C addresses. The WQFN chip has a chip address of 60'h, while the DSBGA chip has a chip address of 61'h. Figure 41. I2C Chip Address (see note above) w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = LP3907 WQFN chip address: 0x60; DSBGA chip address: 0x61 Figure 42. I2C Write Cycle When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. Figure 43. I2C Read Cycle |
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