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LP3907TL-JSXS/NOPB Datasheet(PDF) 40 Page - Texas Instruments |
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LP3907TL-JSXS/NOPB Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 58 page  LP3907 VINLDO1 SDA GND_L LDO1 ENLDO1 SCL VIN1 LDO2 SW2 FB2 VIN2 GND_SW2 ENSW1 ENSW2 VINLDO2 EN_T ENLDO2 GND_C AVDD VINLDO12 DAP 0.47 PF 1 PF 1 PF 0.47 PF 2.2 PH 10 PF 10 PF 1 PF 1 PF 10 PF GND_SW1 SW1 FB1 10 PF 2.2 PH nPOR VDD 100k Copyright © 2016, Texas Instruments Incorporated 40 LP3907 SNVS511S – JUNE 2007 – REVISED APRIL 2016 www.ti.com Product Folder Links: LP3907 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LP3907 provides three control methods to turn ON/OFF four power rails: 1. EN_T Control: Provides pre-defined power up/down sequence. (Note: VIN/Battery voltage must be settled approximately 8 ms, minimum, before EN_T be asserted high). 2. Individual GPIO/EN pin control: four EN pins provide max control flexibility without I2C. 3. I2C control: besides simple ON/OFF control, also provides access to all the user programmable registers. See Register Maps for details. 9.2 Typical Application Figure 45. LP3907 Typical Application 9.2.1 Design Requirements Ten ceramic capacitors and two inductors are required for this application. These three external components must be selected very carefully for property operation. See Detailed Design Procedure. |
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