LP3907TL-JSXSSLASHNOPB datasheet(46/58 Pages) TI1

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LP3907

SNVS511S – JUNE 2007 – REVISED APRIL 2016

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10 Power Supply Recommendations

If the EN_T is used to power up the device instead individual ENs , then VIN must be stable for approximately 8

ms minimum before EN_T be asserted high to ensure internal bias, reference, and the Flexible POR timing are

stabilized. This initial EN_T delay is necessary only upon first time device power on for power sequencing

function to operate properly.

10.1 Analog Power Signal Routing

All power inputs must be tied to the main VDD source (for example, battery), unless the user wishes to power it

from another source. (that is, external LDO output).

The analog VDD inputs power the internal bias and error amplifiers, so they must be tied to the main VDD. The

analog VDD inputs must have an input voltage between 2.8 V and 5.5 V, as specified in the Recommended

Operating Conditions (Bucks) table earlier in the data sheet.

The other VINs (VINLDO1, VINLDO2) can have inputs lower than 2.8 V, as long as the input it higher than the

programmed output (0.3 V).

The analog and digital grounds must be tied together outside of the chip to reduce noise coupling.

LP3907TL-JSXS/NOPB Datasheet(PDF) 46 Page - Texas Instruments