M37207M8-059SP datasheet(30/121 Pages) MITSUBISHI

30 / 121 page

MITSUBISHI MICROCOMPUTERS

M37207MF-XXXSP/FP, M37207M8-XXXSP

M37207EFSP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

and ON-SCREEN DISPLAY CONTROLLER

(1) I2C Data Shift Register

The I2C data shift register (S0 : address 00D916) is an 8-bit shift

When transmit data is written into this register, it is transferred to the

outside from bit 7 in synchronization with the SCL clock, and each

time one-bit data is output, the data of this register are shifted one bit

to the left. When data is received, it is input to this register from bit 0

in synchronization with the SCL clock, and each time one-bit data is

input, the data of this register are shifted one bit to the left.

The I2C data shift register is in a write enable status only when the

ESO bit of the I2C control register (address 00DC16) is “1.” The bit

counter is reset by a write instruction to the I2C data shift register.

When both the ESO bit and the MST bit of the I2C status register

(address 00F816) are “1,” the SCL is output by a write instruction to

the I2C data shift register. Reading data from the I2C data shift regis-

ter is always enabled regardless of the ESO bit value.

Note: To write data into the I2C data shift register after setting the

MST bit to “0” (slave mode), keep an interval of 8 machine

cycles or more.

Fig. 24. I2C Data Shift Register

Fig. 25. I2C Address Register

(2) I2C Address Register

The I2C address register (address 00DA16) consists of a 7-bit slave

___

address and a read/write bit. In the addressing mode, the slave ad-

dress written in this register is compared with the address data to be

received immediately after the START condition are detected.

____

sBit 0: Read/Write Bit (RBW)

Not used when comparing addresses, in the 7-bit addressing mode.

In the 10-bit addressing mode, the first address data to be received

is compared with the contents (SAD6 to SAD0 + RBW) of the I2C

address register.

The RBW bit is cleared to “0” automatically when the stop condition

is detected.

sBits 1 to 7: Slave Address (SAD0–SAD6)

These bits store slave addresses. Regardless of the 7-bit address-

ing mode and the 10-bit addressing mode, the address data trans-

mitted from the master is compared with the contents of these bits.

b7 b6 b5 b4 b3 b2 b1 b0

I C data shift register1(S0) [Address 00D9 16]

Functions

After reset

R W

I C Data Shift Register

This is an 8-bit shift register to store

receive data and write transmit data.

Indeterminate

Note:

To write data into the I C data shift register after setting the MST bit to

“0” (slave mode), keep an interval of 8 machine cycles or more.

Name

D0 to D7

b7 b6 b5 b4 b3 b2 b1 b0

Read/write bit

(RBW)

Slave address

(SAD0 to SAD6)

0: Read

1: Write

The address data transmitted from

the master is compared with the

contents of these bits.

I2C Address Register

I2C address register (S0D) [Address 00DA16]

Name

Functions

After reset

R—

M37207M8-059SP Datasheet(PDF) 30 Page - Mitsubishi Electric Semiconductor

M37207M8-059SP Datasheet(HTML) 30 Page - Mitsubishi Electric Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL