M37207M8-059SP datasheet(36/121 Pages) MITSUBISHI

36 / 121 page

MITSUBISHI MICROCOMPUTERS

M37207MF-XXXSP/FP, M37207M8-XXXSP

M37207EFSP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

and ON-SCREEN DISPLAY CONTROLLER

(9) START/STOP Condition Detect Conditions

The START/STOP condition detect conditions are shown in

Figure 33 and Table 4. Only when the 3 conditions of Table 4 are

satisfied, a START/STOP condition can be detected.

Note: When a STOP condition is detected in the slave mode

(MST = 0), an interrupt request signal “IICIRQ” is generated

to the CPU.

(8) STOP Condition Generation Method

When the ES0 bit of the I2C control register (address 00DC16) is “1,”

execute a write instruction to the I2C status register (address 00DB16)

for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A

STOP condition will then be generated. The STOP condition genera-

tion timing and the BB flag reset timing are different in the standard

clock mode and the high-speed clock mode. Refer to Figure 32 for

the STOP condition generation timing diagram, and Table 3 for the

START condition/STOP condition generation timing table.

Fig. 32. STOP Condition Generation Timing Diagram

Fig. 33. START Condition/STOP Condition Detect Timing

Diagram

Table 4. START Condition/STOP Condition Detect Conditions

Table 3. START Condition/STOP Condition Generation Timing

Table

Item

Setup time

Hold time

Set/reset time

for BB flag

Standard Clock Mode

5.0 µs (20 cycles)

3.0 µs (12 cycles)

High-speed Clock Mode

2.5 µs (10 cycles)

1.5 µs (6 cycles)

Note: Absolute time at

φ = 4 MHz. The value in parentheses de-

notes the number of

φ cycles.

I2C status register

write signal

Reset time for

BB flag

Hold time

Setup

time

SCL

SDA

BB flag

Hold time

Setup

time

SCL

SDA

(START condition)

SDA

(STOP condition)

SCL release time

Hold time

Setup

time

(6) START Condition Generation Method

When the ESO bit of the I2C control register (address 00DC16) is “1,”

execute a write instruction to the I2C status register (address 00DB16)

to set the MST, TRX and BB bits to “1.” A START condition will then

be generated. After that, the bit counter becomes “0002” and an SCL

for 1 byte is output. The START condition generation timing and BB

bit set timing are different in the standard clock mode and the high-

speed clock mode. Refer to Figure 31 for the START condition gen-

eration timing diagram, and Table 3 for the START condition/STOP

condition generation timing table.

Fig. 31. START Condition Generation Timing Diagram

(7) RESTART Condition Generation Method

To generate the RESTART condition, take the following sequence:

Set “2016” to the I2C status register (S1).

Write a transmit data to the I2C data shift register.

Set “F016” to the I2C status register (S1) again.

I2C status register

; S1 = 2016

I2C data shift register ; S0 = transmit data after restart

I2C status register

; S1 = F016

I2C status register

write signal

Set time for

BB flag

Hold time

Setup

time

SCL

SDA

BB flag

Setup

time

Standard Clock Mode

6.5 µs (26 cycles) < SCL

release time

3.25 µs (13 cycles) < Setup time

3.25 µs (13 cycles) < Hold time

High-speed Clock Mode

1.0 µs (4 cycles) < SCL

release time

0.5 µs (2 cycles) < Setup time

0.5 µs (2 cycles) < Hold time

Note: Absolute time at

φ = 4 MHz. The value in parentheses de-

notes the number of

φ cycles.

M37207M8-059SP Datasheet(PDF) 36 Page - Mitsubishi Electric Semiconductor

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