M37207M8-059SP datasheet(37/121 Pages) MITSUBISHI

37 / 121 page

MITSUBISHI MICROCOMPUTERS

M37207MF-XXXSP/FP, M37207M8-XXXSP

M37207EFSP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

and ON-SCREEN DISPLAY CONTROLLER

(10) Address Data Communication

There are two address data communication formats, namely, 7-bit

addressing format and 10-bit addressing format. The respective ad-

dress communication formats is described below.

7-bit addressing format

To meet the 7-bit addressing format, set the 10BIT SAD bit of the

I2C control register (address 00DC16) to “0.” The first 7-bit ad-

dress data transmitted from the master is compared with the high-

order 7-bit slave address stored in the I2C address register (ad-

dress 00DA16). At the time of this comparison, address compari-

son of the RBW bit of the I2C address register (address 00DA16)

is not made. For the data transmission format when the 7-bit ad-

dressing format is selected, refer to Figure 34, (1) and (2).

10-bit addressing format

To meet the 10-bit addressing format, set the 10BIT SAD bit of the

I2C control register (address 00DC16) to “1.” An address compari-

son is made between the first-byte address data transmitted from

the master and the 7-bit slave address stored in the I2C address

dress comparison between the RBW bit of the I2C address regis-

ter (address 00DA16) and the R/W bit which is the last bit of the

address data transmitted from the master is made. In the 10-bit

addressing mode, the R/W bit which is the last bit of the address

data not only specifies the direction of communication for control

data but also is processed as an address data bit.

When the first-byte address data matches the slave address, the

AAS bit of the I2C status register (address 00DB16) is set to “1.” After

the second-byte address data is stored into the I2C data shift register

(address 00D916), make an address comparison between the sec-

ond-byte data and the slave address by software. When the address

data of the 2nd bytes matches the slave address, set the RBW bit of

the I2C address register (address 00DA16) to “1” by software. This

processing can match the 7-bit slave address and R/W data, which

are received after a RESTART condition is detected, with the value

of the I2C address register (address 00DA16). For the data transmis-

sion format when the 10-bit addressing format is selected, refer to

Figure 34, (3) and (4).

(11) Example of Master Transmission

An example of master transmission in the standard clock mode, at

the SCL frequency of 100 kHz and in the ACK return mode is shown

below.

Set a slave address in the high-order 7 bits of the I2C address

Set the ACK return mode and SCL = 100 kHz by setting “8516” in

the I2C clock control register (address 00DD16).

Set “1016” in the I2C status register (address 00DB16) and hold

the SCL at the HIGH.

Set a communication enable status by setting “4816” in the I2C

control register (address 00DC16).

Set the address data of the destination of transmission in the high-

order 7 bits of the I2C data shift register (address 00D916) and set

“0” in the least significant bit.

Set “F016” in the I2C status register (address 00DB16) to generate

a START condition. At this time, an SCL for 1 byte and an ACK

clock automatically occurs.

Set transmit data in the I2C data shift register (address 00D916).

At this time, an SCL and an ACK clock automatically occurs.

When transmitting control data of more than 1 byte, repeat step

Set “D016” in the I2C status register (address 00DB16). After this,

if ACK is not returned or transmission ends, a STOP condition will

be generated.

(12) Example of Slave Reception

An example of slave reception in the high-speed clock mode, at the

SCL frequency of 400 kHz, in the ACK non-return mode, using the

addressing format, is shown below.

Set a slave address in the high-order 7 bits of the I2C address

Set the no ACK clock mode and SCL = 400 kHz by setting “2516”

in the I2C clock control register (address 00DD16).

Set “1016” in the I2C status register (address 00DB16) and hold

the SCL at the HIGH.

Set a communication enable status by setting “4816” in the I2C

control register (address 00DC16).

When a START condition is received, an address comparison is

made.

•When all transmitted addresses are “0” (general call) :

AD0 of the I2C status register (address 00DB16) is set to “1” and

an interrupt request signal occurs.

•When the transmitted addresses match the address set in

AAS of the I2C status register (address 00DB16) is set to “1” and

an interrupt request signal occurs.

•In the cases other than the above :

AD0 and AAS of the I2C status register (address 00DB16) are

set to “0” and no interrupt request signal occurs.

Set dummy data in the I2C data shift register (address 00D916).

When receiving control data of more than 1 byte, repeat step

When a STOP condition is detected, the communication ends.

M37207M8-059SP Datasheet(PDF) 37 Page - Mitsubishi Electric Semiconductor

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