AM7968-125JC datasheet(82/127 Pages) AMD

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TAXIchip Integrated Circuits Technical Manual

X1 is connected to a common Crystal Oscillator or a TTL Clock Source. It is not

recommended that X1 be connected to another Receiver’s CLK output.

X2 is grounded.

The DMS pins of all TAXls must be tied in the same state as the DMS pins on the

Transmitters.

The CSTRB/DSTRB pins on each of the Receivers are all active simultaneously. A

timing description for CSTRB and DSTRB is included in Appendix C, TAXI TIP #89-10

TAXI receiver CSTRB and DSTRB pulse width.

The VLTN pin has timing that is identical to the timing of the Data Out and the Com-

mand Out lines. Its connections are specific to each user’s applications.

If CNB is HIGH, the Receiver will catch the next valid byte of data and hold it. It will not

attempt to catch any more data until it sees a Sync command from the Transmitter or

until its CNB goes LOW and then HIGH again.

Figure 7-3

Receivers in Cascade Mode

CSTRB CMD DATA DSTRB VLTN

CNB

DMS

CLK

IGM

VCC

SERIN+

SERIN–

SERIN+

SERIN–

CSTRB CMD DATA DSTRB VLTN

CNB

DMS

IGM

CSTRB CMD DATA DSTRB VLTN

CNB

DMS

IGM

N/C

SERIN–

SERIN+

RX1

RX2

RX3

Am7969

PRIMARY RX

12.5 MHz

Crystal

OSC

D23-D16

D15-D8

D7-D0

*Transmission line terminations not shown.

12330E-25

The following section describes the functionality of individual pins:

The DSTRB Pin

Any one of the DSTRBs may be used as the user’s DSTRB to his system. When an

entire word has been received (signified internally by a Sync from the Transmitter) the

data in the Receivers are latched out to the output ports and all the DSTRBs are raised

(simultaneously) one cycle later. Likewise, if Commands are sent as part of the cascade

word, the CSTRB/DSTRB connections must be made appropriately.

Timing description for receivers in cascade mode is included in Figure 7-4.

AM7968-125JC Datasheet(PDF) 82 Page - Advanced Micro Devices

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