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AM7968-125JC Datasheet(PDF) 54 Page - Advanced Micro Devices |
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AM7968-125JC Datasheet(HTML) 54 Page - Advanced Micro Devices |
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54 / 127 page ![]() 50 Publication# 12330 Rev. E Amendment /0 Issue Date: April 1994 TAXIchipTM Integrated Circuits Technical Manual 1.0 INTRODUCTION Modern electronic systems move data from point-to-point across physical layer bounda- ries using either serial or parallel data links. Parallel data links provide fast data transfers and are compatible with most computer architectures. However, conventional parallel data links are burdened with cost/performance issues such as costly multi-con- ductor cables, crosstalk, RFI, bit-to-bit skew and other concerns associated with multiple wire interfaces. Serial data links, although simpler and less costly, have not provided sufficient bandwidth to compete with the high data transfer rates of parallel links. Recent technological advances have altered the cost performance trade-off between serial and parallel data transfer techniques. A new chip set from Advanced Micro Devices offers a high performance integrated alternative to traditional serial/parallel data transfer techniques. The TAXlchip set (Transparent Asynchronous Xmitter-Receiver Interface) provides the means to establish a transparent high speed serial link between two high performance parallel buses. The TAXlchip set consists of a Transmitter, which takes parallel data and transmits it serially at up to 175 MHz, and a Receiver, which converts the serial data stream back to parallel form. TAXlchips provide a simple parallel interface through a high speed serial link, while maintaining the data bandwidth required by the system. 1.1 The Am7968 TAXI Transmitter The TAXITM Transmitter consists of an input latch, an encoder, a parallel to serial shift register, a multiplying Phase Locked Loop (PLL), and some control logic (Figure 1-1). Data are input to the latch, encoded, and shifted out at the serial data rate. The encod- ing used is the efficient 4B/5B scheme specified for the ANSI X3T9.5 Fiber Distributed Data Interface (FDDI specification). This encoding divides an 8-bit byte into two, 4-bit nibbles. Each nibble is encoded into a 5-bit symbol. The 10-bit encoded byte is format- ted into an NRZI data stream for output to the media. This 4B/5B encoding is 80% efficient, using a 125 Mbaud transmission rate to send 100 Mbps of data. The Am7968 Transmitter has differential pseudo-ECL (referenced to +5 V) outputs which can drive 50 Ω lines. This capability makes it easy to directly interface with shielded twisted pair or coaxial cables. The pseudo-ECL outputs are also compatible with the ECL interface of optical compo- nents used to drive fiber optic cable. In addition to providing high bandwidth and low attenuation, fiber optic data transmission also offers noise immunity, eliminates RFI and provides data security. Declining optical components costs are bringing the advantages of fiber optic data transmission to an ever wider range of applications, from process control to avionics. The TAXlchip set is the ideal complement for fiber optic interfaces. |
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