AM7968-125JC datasheet(64/127 Pages) AMD

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TAXIchip Integrated Circuits Technical Manual

4.1.1 Local Mode Transmitters

In Local mode, X1 and X2 are the crystal oscillator inputs. The external component

connections are shown in Figure 4-1. Zero temperature coefficient capacitors (type

NPO) should be used for good temperature stability.

Typical Crystal Specification

Fundamental Frequency

4.0 MHz –17.5 MHz +0.1%

Resonant Mode

Parallel

Load Capacitor (Correlation)

30 pF

Operating Temperature Range

°C to 70°C

Temperature Stability

±1.00 ppm

Drive Level (Correlation)

2 mW

Effective Series Resistance

Ω (max)

Holder Type

Low Profile

Aging for 10 Years

±10 ppm

Figure 4-1

TAXlchip Crystal Connection

RESET

Am7968 or, Am7969

C = 150 pF for a 12.5 – 17.5 MHz Crystal, 220 pF for a 4 MHz–12.5 MHz Crystal

12330E-5

The Transmitter may also be run in local mode by applying a TTL frequency source to

X1 and grounding X2. The TTL source may be either from a crystal oscillator module, or

from a neighboring TAXI Transmitter CLK output. In local mode, CLK is the buffered

output of the internal crystal oscillator. Connecting the CLK output of a TAXI Receiver

directly to the X1 input of a TAXI Transmitter is not recommended, because the

Transmitter’s clock stability and jitter requirements are not satisfied by the Receiver CLK

output.

4.2 TAXI Receiver Clock Connections

The considerations and connections for the TAXI Receiver are similar to those for the

TAXI Transmitter. The Receiver X1 and X2 inputs connect to an on-chip oscillator,

whose frequency is determined by a parallel resonant crystal, or is driven by an external

TTL frequency source. The oscillator provides the reference, which sets the expected

center frequency for the data synchronizing PLL. The synchronizing PLL tracks the

incoming data and generates a bit clock from the serial data stream. All of the internal

TAXI Receiver logic, including the logic that generates the CLK output, runs on this bit

rate clock. This recovered clock is as stable as possible in both frequency and phase, as

it tracks the incoming data stream. In addition to the bit synchronization accomplished

by the PLL, the logic will maintain byte synchronization (framing) with the incoming data

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