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MPC8314EVRADDA Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc |
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MPC8314EVRADDA Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc |
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18 / 101 page ![]() MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2 18 Freescale Semiconductor DDR and DDR2 SDRAM 7.2 DDR and DDR2 SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface. 7.2.1 DDR and DDR2 SDRAM Input AC Timing Specifications This table lists the input AC timing specifications for the DDR2 SDRAM (GVDD(typ) = 1.8 V). This table lists the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V. The following two tables list the input AC timing specifications for the DDR SDRAM interface. Note: 1. The voltage regulator for MVREF must be able to supply up to 500 A current. Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions with GVDD of 1.8V ± 100 mV Parameter Symbol Min Max Unit Note AC input low voltage VIL — MVREF – 0.45 V — AC input high voltage VIH MVREF + 0.45 — V — Table 17. DDR SDRAM Input AC Timing Specifications for 2.5 V Interface At recommended operating conditions with GVDD of 2.5V ± 200 mV Parameter Symbol Min Max Unit Note AC input low voltage VIL — MVREF – 0.51 V AC input high voltage VIH MVREF + 0.51 — V Table 18. DDR2 SDRAM Input AC Timing Specifications At recommended operating conditions with GVDD of (1.8 V± 100 mV) Parameter Symbol Min Max Unit Note Controller Skew for MDQS—MDQ 266 MHz 200 MHz tCISKEW –875 –1250 875 1250 ps 1, 2, 3 Note: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit to be captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. 3. Memory controller ODT value of 150 is recommended. Table 19. DDR SDRAM Input AC Timing Specifications At recommended operating conditions with GVDD of (2.5V ± 200 mV) Parameter Symbol Min Max Unit Note Table 15. Current Draw Characteristics for MVREF Parameter / Condition Symbol Min Max Unit Note |
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