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R8C/13 Datasheet(PDF) 110 Page - Renesas Technology Corp |
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R8C/13 Datasheet(HTML) 110 Page - Renesas Technology Corp |
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110 / 224 page ![]() Rev.1.20 Jan 27, 2006 page 99 of 205 REJ09B0111-0120 R8C/13 Group Figure 12.26 TYZMR Register and PUM Register in Programmable Wait One-shot Generation Mode 12.3 Timer (Timer Z) Timer Y, Z mode register SymbolAddressAfter reset TYZMR008016 002 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 TZMOD1 TYS TYWC TYMOD0 TZMOD0 Timer Y-related bit TZWC TZS 0 : Stops counting 1 : Starts counting Timer Z count start flag Timer Z operation mode bit b5 b4 Timer Z write control bit 1 NOTES: 1. When the TZS bit is set to "0" (stop counting), the timer reloads the content of the reload register before it stops. Read out the count value before you stop the timer. RW RW RW RW RW RW RW RW R1EDG RW Must set to "1" in programmable wait one-shot generation mode 1 1 1 1 : Programmable wait one-shot generation mode Bit name Function Bit symbol Timer Y, Z waveform output control register Symbol Address After reset PUM 008416 0016 b7 b6 b5 b4 b3 b2 b1 b0 TYOPL TZOPL INOSEG INOSTG INT0 pin one-shot trigger polarity select bit(1) Timer Z output level latch Timer Y-related bit INT0 pin one-shot trigger control bit(2) Reserved bit Must set to “0” (b3-b0) RW RW RW RW RW RW 0 0 0 0 0 : Edge trigger at falling edge 1 : Edge trigger at rising edge 0 : Outputs "H" level one-shot pulse. Outputs "L" when the timer is stopped. 1 : Outputs "L" level one-shot pulse Outputs "H" when the timer is stopped. 0 : INT0 pin one-shot trigger disabled 1 : INT0 pin one-shot trigger enabled(2) NOTES: 1. The INOSEG bit is valid only when the INT0PL bit in the INTEN register is set to "0" (one-edge). 2. The INOSGT bit must be set to “1” after the INT0EN bit the INOSEG register and the INOSEG bit in the PUM register are set. When setting the INOSTG bit to "1" (INT0 pin one-shot trigger enabled), the INT0F0 and INT0F1 bits in the INT0F register must be set. The INOSTG bit must be set to “0” (INT0 pin one-shot trigger disabled) after the TZS bit in the TYZMR register is set to “0” (count stop). |
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