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R8C/13 Datasheet(PDF) 102 Page - Renesas Technology Corp

Part # R8C/13
Description  16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
PDF  224 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R8C/13 Datasheet(HTML) 102 Page - Renesas Technology Corp

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Rev.1.20
Jan 27, 2006
page 91 of 205
REJ09B0111-0120
R8C/13 Group
12.3.1 Timer Mode
In this mode, the timer counts an internally generated count source or Timer Y underflow (see “Table
12.9 Timer Mode Specifications”). The TZSC register is unused in timer mode. Figure 12.22 shows
the TYZMR register and PUM register in timer mode.
Item
Specification
Count source
f1, f2, f8, Timer Y underflow
Count operation
• Down-count
• When the timer underflows, it reloads the reload register contents before continuing
counting (When the Timer Z underflows, the contents of the Timer Z primary reload
register is reloaded.)
Divide ratio
1/(n+1)(m+1)
n: set value in PREZ register, m: set value in TZPR register
Count start condition
Write “1” (count start) to TZS bit in TYZMR register
Count stop condition
Write “0” (count stop) to TZS bit in TYZMR register
Interrupt request
• When Timer Z underflows [Timer Z interrupt]
generation timing
TZOUT pin function
Programmable I/O port
_______
INT0 pin function
______
Programmable I/O port, or INT0 interrupt input
Read from timer
Count value can be read out by reading TZPR register.
Same applies to PREZ register.
Write to timer(1)
Value written to TZPR register is written to both reload register and counter or written to
reload register only. Selected by program.
Same applies to PREZ register.
NOTES:
1. The IR bit in the TZIC register is set to "1" (interrupt requested) if you write to the TZPR or PREZ register while both
of the following conditions are met.
<Conditions>
• TZWC bit in TYZMR register is set to "0" (write to reload register and counter simultaneously)
• TZS bit in TYZMR register is set to "1" (count start)
To write to the TZPR or PREZ register in the above state, disable interrupts before the writing.
Table 12.9 Timer Mode Specifications
12.3 Timer (Timer Z)



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