HD6432138SW datasheet(333/1061 Pages) RENESAS

333 / 1061 page

Section 11 16-Bit Free-Running Timer

Rev. 4.00 Jun 06, 2006 page 279 of 1004

REJ09B0301-0400

Timing is described in section 11.3, Operation.

Bit 7—Input Capture Flag A (ICFA): This status flag indicates that the FRC value has been

transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that

the old ICRA value has been moved into ICRC and the new FRC value has been transferred to

ICRA.

ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.

Bit 7

ICFA

Description

[Clearing condition]

Read ICFA when ICFA = 1, then write 0 in ICFA

(Initial value)

[Setting condition]

When an input capture signal causes the FRC value to be transferred to

ICRA

Bit 6—Input Capture Flag B (ICFB): This status flag indicates that the FRC value has been

transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that

the old ICRB value has been moved into ICRD and the new FRC value has been transferred to

ICRB.

ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.

Bit 6

ICFB

Description

[Clearing condition]

Read ICFB when ICFB = 1, then write 0 in ICFB

(Initial value)

[Setting condition]

When an input capture signal causes the FRC value to be transferred to ICRB

Bit 5—Input Capture Flag C (ICFC): This status flag indicates that the FRC value has been

transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of the

signal transition in FTIC (input capture signal) specified by the IEDGC bit, ICFC is set but data is

not transferred to ICRC. Therefore, in buffer operation, ICFC can be used as an external interrupt

signal (by setting the ICICE bit to 1).

ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.

HD6432138SW Datasheet(PDF) 333 Page - Renesas Technology Corp