HD6432138SW datasheet(337/1061 Pages) RENESAS

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Section 11 16-Bit Free-Running Timer

Rev. 4.00 Jun 06, 2006 page 283 of 1004

REJ09B0301-0400

Bit 4—Input Edge Select D (IEDGD): Selects the rising or falling edge of the input capture D

signal (FTID).

Bit 4

IEDGD

Description

Capture on the falling edge of FTID

(Initial value)

Capture on the rising edge of FTID

Bit 3—Buffer Enable A (BUFEA): Selects whether ICRC is to be used as a buffer register for

ICRA.

Bit 3

BUFEA

Description

ICRC is not used as a buffer register for input capture A

(Initial value)

ICRC is used as a buffer register for input capture A

Bit 2—Buffer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for

ICRB.

Bit 2

BUFEB

Description

ICRD is not used as a buffer register for input capture B

(Initial value)

ICRD is used as a buffer register for input capture B

Bits 1 and 0—Clock Select (CKS1, CKS0): Select external clock input or one of three internal

clock sources for the FRC. External clock pulses are counted on the rising edge of signals input to

the external clock input pin (FTCI).

Bit 1

Bit 0

CKS1

CKS0

Description

φ/2 internal clock source

(Initial value)

φ/8 internal clock source

φ/32 internal clock source

External clock source (rising edge)

HD6432138SW Datasheet(PDF) 337 Page - Renesas Technology Corp