HD6432138SW datasheet(336/1061 Pages) RENESAS

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Section 11 16-Bit Free-Running Timer

Rev. 4.00 Jun 06, 2006 page 282 of 1004

REJ09B0301-0400

11.2.8

Timer Control Register (TCR)

Bit

Initial value

Read/Write

IEDGA

R/W

IEDGB

R/W

IEDGC

R/W

IEDGD

R/W

BUFEA

R/W

CKS0

R/W

BUFEB

R/W

CKS1

R/W

TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture

signals, enables the input capture buffer mode, and selects the FRC clock source.

TCR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A

signal (FTIA).

Bit 7

IEDGA

Description

Capture on the falling edge of FTIA

(Initial value)

Capture on the rising edge of FTIA

Bit 6—Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B

signal (FTIB).

Bit 6

IEDGB

Description

Capture on the falling edge of FTIB

(Initial value)

Capture on the rising edge of FTIB

Bit 5—Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C

signal (FTIC).

Bit 5

IEDGC

Description

Capture on the falling edge of FTIC

(Initial value)

Capture on the rising edge of FTIC

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