HD6432138SW datasheet(329/1061 Pages) RENESAS

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Section 11 16-Bit Free-Running Timer

Rev. 4.00 Jun 06, 2006 page 275 of 1004

REJ09B0301-0400

Table 11.3

Buffered Input Capture Edge Selection (Example)

IEDGA

IEDGC

Description

Captured on falling edge of input capture A (FTIA)

(Initial value)

Captured on both rising and falling edges of input capture A (FTIA)

Captured on rising edge of input capture A (FTIA)

To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock

periods (1.5

φ). When triggering is enabled on both edges, the input capture pulse width should be

at least 2.5 system clock periods (2.5

φ).

ICR is initialized to H'0000 by a reset and in hardware standby mode.

11.2.4

Output Compare Registers AR and AF (OCRAR, OCRAF)

Bit

Initial

R/W

value

Write

Read/

OCRAR and OCRAF are 16-bit readable/writable registers.

When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use

of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added

alternately to OCRA, and the result is written to OCRA. The write operation is performed on the

occurrence of compare-match A. In the first compare-match A after the OCRAMS bit is set to 1,

OCRAF is added.

The operation due to compare-match A varies according to whether the compare-match follows

addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output

on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A

following addition of OCRAR.

When the OCRA automatically addition function is used, do not set internal clock

φ/2 as the FRC

counter input clock together with an OCRAR (or OCRAF) value of H'0001 or less.

OCRAR and OCRAF are initialized to H'FFFF by a reset and in hardware standby mode.

HD6432138SW Datasheet(PDF) 329 Page - Renesas Technology Corp